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19 lines
552 B
Systemverilog
19 lines
552 B
Systemverilog
// DESCRIPTION: Verilator: Test of Verilog and SystemVerilog integer literal differences
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Ethan Sifferman.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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// "unbased_unsized_literal" is SystemVerilog only
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// Should fail with "NEWERSTD"
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wire [127:0] FOO1 = '0;
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wire [127:0] FOO2 = '1;
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wire [127:0] FOO3 = 'x;
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wire [127:0] FOO4 = 'X;
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wire [127:0] FOO5 = 'z;
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wire [127:0] FOO6 = 'Z;
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endmodule
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