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37 lines
1005 B
Systemverilog
37 lines
1005 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire[3:0] #4 val1 = half_cyc;
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wire[3:0] #4 val2;
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reg[3:0] half_cyc = 0;
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assign #4 val2 = half_cyc;
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always @(clk) begin
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if ($time > 0) half_cyc <= half_cyc + 1;
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`ifdef TEST_VERBOSE
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$strobe("[%0t] half_cyc=%0d, val1=%0d, val2=%0d", $time, half_cyc, val1, val2);
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`endif
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if (half_cyc >= 7) begin
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`checkh(val1, half_cyc - 3);
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`checkh(val2, half_cyc - 7);
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end
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if (half_cyc == 15) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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