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31 lines
692 B
Systemverilog
31 lines
692 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off DECLFILENAME
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module t(/*AUTOARG*/);
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mailbox #(int) m;
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int msg = 0;
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int out = 0;
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initial begin
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m = new;
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fork
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begin
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#10; // So later then get() starts below
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msg = 1;
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if (m.try_put(msg) != 1) $stop;
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end
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begin
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m.get(out);
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if (out != 1) $stop;
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end
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join
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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