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3f89bdcfac
No functional change. Postpone the conversion of all AstAssignDlys that use the 'VdlySet' scheme for array LHSs until after the complete traversal of the netlist. The next patch takes advantage of this by using some extra information also gathered through the traversal to change the conversion. AstAssignDlys inside suspendable or fork are not deferred and are processed identical to the previous version. There are some TODOs in this patch that are fixed in the next patch. Output code perturbed due to variable ordering. MULTIDRIVEN message ordering perturbed due to processing order change.
18 lines
1.0 KiB
Plaintext
18 lines
1.0 KiB
Plaintext
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:22: Signal has multiple driving blocks with different clocking: 'out2'
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t/t_lint_multidriven_bad.v:35:7: ... Location of first driving block
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35 | out2[15:8] <= d0;
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| ^~~~
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t/t_lint_multidriven_bad.v:32:7: ... Location of other driving block
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32 | out2[7:0] <= d0;
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| ^~~~
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... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest
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... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message.
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%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:21:22: Signal has multiple driving blocks with different clocking: 't.mem'
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t/t_lint_multidriven_bad.v:27:7: ... Location of first driving block
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27 | mem[a0] <= d1;
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| ^~~
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t/t_lint_multidriven_bad.v:24:7: ... Location of other driving block
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24 | mem[a0] <= d0;
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| ^~~
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%Error: Exiting due to
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