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51 lines
1.1 KiB
Systemverilog
51 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Do not reindent - spaces are critical to this test
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// verilator lint_off UNUSEDLOOP
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module t (/*AUTOARG*/);
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initial begin
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if (0)
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$display("ok");
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$display("bad1"); // <--- Bad
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if (0)
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$display("ok");
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else
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$display("ok");
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$display("bad2"); // <--- Bad
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for (;0;)
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$display("ok");
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$display("bad3"); // <--- Bad
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while (0)
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$display("ok");
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$display("bad4"); // <--- Bad
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// Normal styles
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if (0) $display("ok");
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$display("ok");
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for (;0;) $display("ok");
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$display("ok");
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while (0) $display("ok");
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$display("ok");
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// Questionable but pops up in some cases e.g. SweRV
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// (all statements have similar indent)
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if (0)
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begin
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$display("ok");
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end
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$display("ok");
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end
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endmodule
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