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37 lines
695 B
Systemverilog
37 lines
695 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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mailbox #(int) mbox;
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task main();
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// See issue #4323; not an INFINITELOOP due to delay inside get()
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forever begin
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int i;
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mbox.get(i);
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$display("[%0t] Got %0d", $time, i);
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end
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endtask
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initial begin
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mbox = new (1);
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#10;
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fork
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main();
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join_none
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#10;
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mbox.put(10);
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mbox.put(11);
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#10;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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