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18 lines
460 B
Systemverilog
18 lines
460 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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let RECURSE(a) = (a == 1) ? 1 : RECURSE(a - 1); // BAD no recursion per IEEE 1800-2023 11.12
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initial begin
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if (RECURSE(1) != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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