verilator/test_regress/t/t_json_only_output.v

11 lines
274 B
Systemverilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module m
(input clk); // verilator tag foo_op
endmodule