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d330100542
Prior to this we failed to create implicit nets for inputs of gate primitives, which is required by the standard (IEEE 1800-2017 6.10). Note: outputs were covered due to being modeled as the LHS of assignments, which do create implicit nets.
102 lines
2.9 KiB
Systemverilog
Executable File
102 lines
2.9 KiB
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc=1;
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// Instantiate the primitive gates to be tested.
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and g_and(o_and, i_and1, i_and2, i_and3);
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not g_not(o_not1, o_not2, i_not1);
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nor g_nor(o_nor, i_nor1, i_nor2, i_nor3);
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or g_or(o_or, i_or1, i_or2, i_or3);
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nand g_nand(o_nand, i_nand1, i_nand2, i_nand3);
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xor g_xor(o_xor, i_xor1, i_xor2, i_xor3);
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xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3);
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buf g_buf(o_buf1, o_buf2, i_buf1);
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bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02);
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bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12);
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notif0 g_notif0(o_notif0, i_notif01, i_notif02);
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notif1 g_notif1(o_notif1, i_notif11, i_notif12);
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// Generate random data for inputs
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reg rd_data1, rd_data2, rd_data3;
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always @(posedge clk) begin
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rd_data1 = 1'($random);
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rd_data2 = 1'($random);
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rd_data3 = 1'($random);
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end
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// Assign the input of primitive gates.
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`default_nettype none
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assign i_and1 = rd_data1;
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assign i_and2 = rd_data2;
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assign i_and3 = rd_data3;
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assign i_not1 = rd_data1;
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assign i_nor1 = rd_data1;
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assign i_nor2 = rd_data2;
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assign i_nor3 = rd_data3;
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assign i_or1 = rd_data1;
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assign i_or2 = rd_data2;
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assign i_or3 = rd_data3;
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assign i_nand1 = rd_data1;
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assign i_nand2 = rd_data2;
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assign i_nand3 = rd_data3;
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assign i_xor1 = rd_data1;
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assign i_xor2 = rd_data2;
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assign i_xor3 = rd_data3;
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assign i_xnor1 = rd_data1;
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assign i_xnor2 = rd_data2;
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assign i_xnor3 = rd_data3;
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assign i_buf1 = rd_data1;
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assign i_bufif01 = rd_data1;
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assign i_bufif02 = rd_data2;
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assign i_bufif11 = rd_data1;
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assign i_bufif12 = rd_data2;
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assign i_notif01 = rd_data1;
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assign i_notif02 = rd_data2;
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assign i_notif11 = rd_data1;
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assign i_notif12 = rd_data2;
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// Check the outputs of the gate instances
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always @(negedge clk) begin
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if (o_and !== (i_and1 & i_and2 & i_and3)) $stop;
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if ((o_not1 !== ~i_not1) || (o_not2 != ~i_not1)) $stop;
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if (o_nor !== !(i_nor1 | i_nor2 | i_nor3)) $stop;
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if (o_or !== (i_or1 | i_or2 | i_or3)) $stop;
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if (o_nand !== !(i_nand1 & i_nand2 & i_nand3)) $stop;
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if (o_xor !== (i_xor1 ^ i_xor2 ^ i_xor3)) $stop;
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if (o_xnor !== !(i_xnor1 ^ i_xnor2 ^ i_xnor3)) $stop;
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if ((o_buf1 !== i_buf1) || (o_buf2 !== i_buf1)) $stop;
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if (!(o_bufif0 == (i_bufif01 & !i_bufif02))) $stop;
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if (!(o_bufif1 == (i_bufif11 & i_bufif12))) $stop;
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if (!(o_notif0 == (!i_notif01 & !i_notif02))) $stop;
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if (!(o_notif1 == (!i_notif11 & i_notif12))) $stop;
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end
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always @(posedge clk) begin
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cyc = cyc + 1;
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if (cyc == 100) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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