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61 lines
1.2 KiB
Systemverilog
61 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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class MyInt;
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int x;
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function new(int a);
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x = a;
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endfunction
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endclass
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function int get_val_set_5(ref int x);
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automatic int y = x;
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x = 5;
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return y;
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endfunction
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class Cls;
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function int get_val_set_2(ref int x);
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automatic int y = x;
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x = 2;
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return y;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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int a, b;
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int arr[1];
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Cls cls;
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MyInt mi;
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initial begin
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a = 10;
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b = get_val_set_5(a);
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`checkh(a, 5);
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`checkh(b, 10);
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cls = new;
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b = cls.get_val_set_2(a);
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`checkh(a, 2);
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`checkh(b, 5);
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mi = new(1);
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b = cls.get_val_set_2(mi.x);
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`checkh(mi.x, 2);
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`checkh(b, 1);
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arr[0] = 10;
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b = cls.get_val_set_2(arr[0]);
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`checkh(arr[0], 2);
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`checkh(b, 10);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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