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57 lines
1.2 KiB
Systemverilog
57 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t();
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typedef integer q_t[$];
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function void queue_set(ref q_t q);
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`ifdef TEST_NOINLINE
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// verilator no_inline_task
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`endif
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q.push_back(42);
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if (q.size() != 1) $stop;
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endfunction
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function void queue_check_nref(q_t q);
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`ifdef TEST_NOINLINE
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// verilator no_inline_task
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`endif
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q[0] = 11;
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if (q[0] != 11) $stop;
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endfunction
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function void queue_check_ref(const ref q_t q);
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`ifdef TEST_NOINLINE
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// verilator no_inline_task
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`endif
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if (q[0] != 42) $stop;
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endfunction
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function q_t queue_ret();
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`ifdef TEST_NOINLINE
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// verilator no_inline_task
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`endif
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queue_ret = '{101};
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endfunction
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initial begin
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q_t iq;
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queue_set(iq);
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if (iq.size() != 1) $stop;
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queue_check_ref(iq);
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iq[0] = 44;
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queue_check_nref(iq);
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if (iq[0] != 44) $stop;
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iq = queue_ret();
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if (iq[0] != 101) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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