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44 lines
1010 B
Systemverilog
44 lines
1010 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t(/*AUTOARG*/);
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int a;
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function int assign5;
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a = 5;
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return 5;
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endfunction
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function int assign3;
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a = 3;
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return 3;
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endfunction
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function int incr;
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a++;
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return a;
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endfunction
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function int assign5_return_arg(int x);
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a = 5;
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return x;
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endfunction
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int i;
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initial begin
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a = 1;
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i = assign5() + assign3() + incr();
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`checkd(a, 4); `checkd(i, 12);
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a = 1;
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i = assign5_return_arg(assign3()+incr());
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`checkd(a, 5); `checkd(i, 7);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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