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108 lines
2.7 KiB
Systemverilog
108 lines
2.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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class Cls;
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enum { ONEK = 1000, TWOK = 2000 } sev_t;
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int m_default_data;
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function int trigger(int data=get_default_data());
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return data;
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endfunction
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task triggert(output int o, input int data=get_default_data());
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o = data;
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endtask
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virtual function int get_default_data();
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return m_default_data;
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endfunction
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function int uvm_report(int severity,
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int verbosity = (severity == 1) ? ONEK : TWOK);
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return verbosity;
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endfunction
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endclass
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module t(/*AUTOARG*/);
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function int mod_trigger(int data=mod_data());
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return data;
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endfunction
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task mod_triggert(output int o, input int data=mod_data());
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o = data;
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endtask
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int mod_default_data;
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function int mod_data();
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return mod_default_data;
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endfunction
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int v;
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initial begin
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begin
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mod_triggert(v, 1234);
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`checkd(v, 1234);
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mod_default_data = 42;
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v = mod_trigger();
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`checkd(v, 42);
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v = mod_trigger(11);
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`checkd(v, 11);
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mod_default_data = 43;
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v = mod_trigger();
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`checkd(v, 43);
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v = mod_trigger(); // Multiple to test look up of duplicates
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`checkd(v, 43);
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mod_default_data = 52;
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mod_triggert(v);
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`checkd(v, 52);
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mod_triggert(v); // Multiple to test look up of duplicates
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`checkd(v, 52);
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end
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begin
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Cls c = new;
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c.m_default_data = 42;
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v = c.trigger();
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`checkd(v, 42);
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v = c.trigger(11);
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`checkd(v, 11);
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c.m_default_data = 43;
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v = c.trigger();
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`checkd(v, 43);
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v = c.trigger(); // Multiple to test look up of duplicates
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`checkd(v, 43);
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v = c.trigger(); // Multiple to test look up of duplicates
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`checkd(v, 43);
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c.m_default_data = 52;
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c.triggert(v);
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`checkd(v, 52);
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c.triggert(v); // Multiple to test look up of duplicates
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`checkd(v, 52);
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v = c.uvm_report(1);
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`checkd(v, 1000);
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v = c.uvm_report(2);
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`checkd(v, 2000);
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v = c.uvm_report(1, 111);
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`checkd(v, 111);
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v = c.uvm_report(1, 222);
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`checkd(v, 222);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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