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48 lines
1.3 KiB
Systemverilog
48 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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logic [3:0] m_mask;
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initial begin
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int i;
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int n = 4;
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m_mask = 0;
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fork
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begin
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fork
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begin
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fork
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begin
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for(i = 0; i < n; i++) begin
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fork
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automatic int k = i;
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begin
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// see issue #4493
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$display("[%0t] start %0d", $time, k);
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// UVM's arb_sequence_q[is_relevant_entries[k]].wait_for_relevant();
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m_mask[k] = 1;
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#1;
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end
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join_none
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wait (m_mask[i]);
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end
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end
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join_any
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end
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join_any
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end
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join
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if (m_mask != {4{1'b1}}) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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