mirror of
https://github.com/verilator/verilator.git
synced 2025-01-05 22:27:35 +00:00
24 lines
466 B
Systemverilog
24 lines
466 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2023 by Antmicro Ltd.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
class bar;
|
|
task foo(logic r);
|
|
int a, b;
|
|
if (r) return;
|
|
fork a = #1 b; join_none
|
|
endtask
|
|
endclass
|
|
|
|
module t;
|
|
bar b = new;
|
|
|
|
initial begin
|
|
b.foo(0);
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
endmodule
|