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745605efe3
DFG could remove forceable signals by replacing them with their in-design driver. This is a bit of a pain to prevent, and ideally the forcing transform should happen before DFG, but implementing it there is a pain due to having to rewrite ports based on direction. This is an attempted fix in DFG. More cases might remain.
224 lines
2.3 KiB
Plaintext
224 lines
2.3 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module top $end
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$var wire 1 # clk $end
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$var wire 1 $ rst $end
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$var wire 32 % cyc [31:0] $end
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$scope module t $end
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$var wire 1 # clk $end
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$var wire 1 $ rst $end
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$var wire 32 % cyc [31:0] $end
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$var wire 1 & net_1 $end
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$var wire 8 ' net_8 [7:0] $end
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$var wire 1 & obs_1 $end
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$var wire 8 ' obs_8 [7:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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0#
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1$
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b00000000000000000000000000000000 %
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1&
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b11111111 '
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#5
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1#
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0$
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#10
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#15
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1#
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b00000000000000000000000000000001 %
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0&
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#20
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b00000000000000000000000000000010 %
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1&
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b11111110 '
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b00000000000000000000000000001111 %
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b00000000000000000000000000011000 %
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b00000000000000000000000000011001 %
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b00000000000000000000000000011111 %
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0&
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