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61 lines
1.4 KiB
Systemverilog
61 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t(/*AUTOARG*/
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// Outputs
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topout,
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// Inputs
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clk, topin
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);
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input clk;
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input [3:0] topin;
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output [3:0] topout;
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integer cyc = 0;
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assign topout = 4'b0101;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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if (topout != 4'b0101) $stop;
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if (topin != 4'b1001) $stop;
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end
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else if (cyc == 1) begin
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force topout = 4'b1010;
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end
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else if (cyc == 2) begin
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if (topout != 4'b1010) $stop;
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release topout;
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end
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else if (cyc == 3) begin
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if (topout != 4'b0101) $stop;
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end
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else if (cyc == 4) begin
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force topin = 4'b1100;
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end
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else if (cyc == 5) begin
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if (topin != 4'b1100) $stop;
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release topin;
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end
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else if (cyc == 6) begin
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if (topin != 4'b1001) $stop;
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end
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//
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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