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https://github.com/verilator/verilator.git
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f3bace10ae
- Enable creating constant pool entries for RHS of simple var = const assignments - Never extract ArraySel (it's just pointer arithmetic) - Remove unnecessary AstTraceInc precond child tree - Always fully recurse expressions (fix transplanted from #4617) - General cleanup Overall the patch is performance neutral to slightly positive, but saves ~10% peak Verialtor memory usage due to not creating temporaries (which are later expanded) for any ArraySels.
21 lines
645 B
Perl
Executable File
21 lines
645 B
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2008 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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compile(
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verilator_flags2 => ['--expand-limit 1 --stats -fno-dfg'],
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);
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file_grep($Self->{stats}, qr/Optimizations, expand limited\s+(\d+)/i, 3);
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ok(1);
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1;
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