verilator/test_regress/t/t_flag_comp_limit_parens.pl
2023-02-26 10:18:40 -05:00

26 lines
731 B
Perl
Executable File

#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2008 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile(
verilator_flags2 => ["--comp-limit-parens 2"],
);
execute(
check_finished => 1,
);
my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root__DepSet*__Slow.cpp");
file_grep_any(\@files, qr/Vdeeptemp/i);
ok(1);
1;