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40 lines
721 B
Systemverilog
40 lines
721 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Based on ivtest's nested_impl_event1.v by Martin Whitaker.
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module t();
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reg a;
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reg b;
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reg c;
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always @* begin // @(b or c)
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a = b;
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$display("[%0t] Triggered 1 @(b or c)", $time);
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@* a = c; // @(c)
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$display("[%0t] Triggered 2 @(c)", $time);
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end
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initial begin
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#10;
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b = 0;
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#10;
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b = 1;
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#10;
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c = 0;
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#10;
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c = 1;
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#10;
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c = 0;
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#10;
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$write("*-* All Finished *-*\n");
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$finish(0);
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end
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endmodule
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