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69 lines
1.3 KiB
Systemverilog
69 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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int evt_recv_cnt;
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int new_evt_recv_cnt;
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module t();
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class Foo;
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event evt1;
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task automatic send_evt();
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fork
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#10 begin ->evt1; end
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begin
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event new_event;
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#20;
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// This should cause an event merge but for now we don't support that.
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evt1 = new_event;
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end
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#30 begin
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@evt1 $display("Received a new event");
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new_evt_recv_cnt++;
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end
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join_none
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endtask
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task wait_for_event();
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fork begin
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@evt1 $display("Received evt1");
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evt_recv_cnt++;
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end join_none
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endtask
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endclass
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initial begin
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Foo foo1;
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foo1 = new;
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evt_recv_cnt = 0;
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new_evt_recv_cnt = 0;
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for (int i = 0; i < 4; i++) begin
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foo1.wait_for_event();
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#10;
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foo1.send_evt();
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#90;
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$display("- end of iteration -");
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if (evt_recv_cnt != i + 1)
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$stop;
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if (new_evt_recv_cnt != i)
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$stop;
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end
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if (evt_recv_cnt != 4)
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$stop;
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if (new_evt_recv_cnt != 3)
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$stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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