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38 lines
790 B
Systemverilog
38 lines
790 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// See issue #2855
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package Pkg;
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typedef enum int unsigned {
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MODE10 = 10
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} mode_t;
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typedef struct packed {
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bit u;
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mode_t a;
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bit b;
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} foo_t;
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localparam foo_t FOO0 = '{a: 0, b: 1'b1, u: 1'b1};
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localparam foo_t FOO1 = '{a: MODE10, b: 1'b1, u: 1'b1};
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endpackage
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module t(/*AUTOARG*/);
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initial begin
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//if (sum !== `EXPECTED_SUM) $stop;
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if (Pkg::FOO0 != {1'b1, 32'd0, 1'b1}) $stop;
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if (Pkg::FOO1 != {1'b1, 32'd10, 1'b1}) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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