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40 lines
918 B
Systemverilog
40 lines
918 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t (/*AUTOARG*/);
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int a1[] = '{12, 13};
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int a2[] = {14, 15};
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int a3[] = '{16};
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int a4[] = {17};
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int a5[] = {};
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initial begin
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`checkh(a1.size, 2);
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`checkh(a1[0], 12);
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`checkh(a1[1], 13);
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`checkh(a2.size, 2);
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`checkh(a2[0], 14);
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`checkh(a2[1], 15);
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`checkh(a3.size, 1);
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`checkh(a3[0], 16);
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`checkh(a4.size, 1);
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`checkh(a4[0], 17);
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`checkh(a5.size, 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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