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cbc76a7816
With --stats, we will print DFG pattern combinations, one per line, as S-expressions to new stat files, together with their frequency, to aid discovery of new peephole patterns.
38 lines
903 B
Systemverilog
38 lines
903 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input wire [3:0] a,
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input wire [3:0] b,
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input wire [3:0] c,
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output wire [3:0] x,
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output wire [3:0] y,
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output wire [3:0] z,
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output wire [ 0:0] w1,
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output wire [ 7:0] w8,
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output wire [15:0] w16,
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output wire [31:0] w32,
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output wire [63:0] w64a,
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output wire [63:0] w64b,
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output wire [62:0] w63,
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output wire [95:0] w96
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);
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assign x = ~a & ~b;
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assign y = ~b & ~c;
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assign z = ~c & ~a;
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assign w1 = x[0];
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assign w8 = {8{x[1]}};
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assign w16 = {2{w8}};
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assign w32 = {2{w16}};
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assign w64a = {2{w32}};
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assign w64b = {2{~w32}};
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assign w63 = 63'({2{~w32}});
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assign w96 = 96'(w64a);
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endmodule
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