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31 lines
662 B
Systemverilog
31 lines
662 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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parameter PDLY = 1.2;
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real rdly = 1.3;
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integer idly = 1;
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reg in = 1'b0;
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wire #1.1 d_const = in;
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wire #idly d_int = in;
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wire #rdly d_real = in;
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wire #PDLY d_param = in;
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initial begin
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#2 in = 1'b1;
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#100;
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if (d_const != 1) $stop;
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if (d_int != 1) $stop;
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if (d_real != 1) $stop;
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if (d_param != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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