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36 lines
777 B
Systemverilog
36 lines
777 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int tim1;
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int tim2;
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real rtim1;
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real rtim2;
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initial begin
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tim1 = 2;
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tim2 = 3;
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// verilator lint_off WIDTHEXPAND
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# (tim1 < tim2);
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// verilator lint_on WIDTHEXPAND
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if ($time != 1) $stop;
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// verilator lint_off WIDTHEXPAND
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# (tim1);
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// verilator lint_on WIDTHEXPAND
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if ($time != 1 + 2) $stop;
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rtim1 = 2;
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rtim2 = 2.6;
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# (rtim1 + rtim2); // Rounds up
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if ($time != 1 + 2 + 5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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