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75 lines
1.3 KiB
Systemverilog
75 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// On some platforms (i.e. FreeBSD 12) this triggered:
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//
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// Active region did not converge.
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//
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// due to the mistaken belief that the AstVarScope node for TOP->t__DOT__clk
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// is equal to the AstVarScope node for TOP->t__DOT__rst. This occured because
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// AstVarScope was missing an appropriate same method and is tickled by the LLVM
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// libcxx library.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by John Wehle.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire [1:0] out;
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reg in;
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reg rst;
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reg clk;
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initial begin
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clk = 0;
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rst = 0;
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#10 rst = 1;
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#10 rst = 0;
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in = 1'b0;
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#30 $write("*-* All Finished *-*\n");
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$finish;
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end
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always begin
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#10 clk <= !clk;
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end
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Test test(.out(out), .in(in),
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.clk(clk), .rst(rst));
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endmodule
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module Test(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, in, rst
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);
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input clk;
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input in;
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input rst;
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output wire [1:0] out;
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reg [1:0] s;
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reg sin;
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assign out = s;
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always @(posedge clk)
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begin
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s[1] <= in;
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s[0] <= sin;
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end
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always @(negedge clk, posedge rst)
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if (rst)
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sin <= 1'b0;
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else
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sin <= in;
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endmodule
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