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40 lines
854 B
Systemverilog
40 lines
854 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Baz;
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endclass
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class Bar#(type T) extends T;
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endclass
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class Foo;
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typedef struct {
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int field;
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} Zee;
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task t1();
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// Refer to Baz CLASSREFDTYPE node in implementation (via CLASSEXTENDS)
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Bar#(Baz) b = new;
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endtask
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// Refer to the very same Baz CLASSREFDTYPE node again, this time within interface
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task t2(Bar#(Baz)::T b);
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endtask
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endclass
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class Moo;
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// Use Foo::Zee to cause inclusion of Foo's header file
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Foo::Zee z;
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endclass
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module t();
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initial begin
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// Use Moo in top module to add Moo to root, causing inclusion of Foo header into
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// root header.
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Moo moo;
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moo = new;
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end
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endmodule
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