mirror of
https://github.com/verilator/verilator.git
synced 2025-01-21 05:44:03 +00:00
176 lines
9.0 KiB
XML
176 lines
9.0 KiB
XML
<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="<built-in>" language="1800-2023"/>
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<file id="b" filename="<command-line>" language="1800-2023"/>
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<file id="c" filename="input.vc" language="1800-2023"/>
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<file id="d" filename="t/t_constraint_xml.v" language="1800-2023"/>
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</files>
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<module_files>
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<file id="d" filename="t/t_constraint_xml.v" language="1800-2023"/>
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</module_files>
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<cells>
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<cell loc="d,65,8,65,9" name="t" submodname="t" hier="t"/>
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</cells>
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<netlist>
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<module loc="d,65,8,65,9" name="t" origName="t">
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<var loc="d,67,11,67,12" name="p" dtype_id="1" vartype="Packet" origName="p"/>
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<initial loc="d,69,4,69,11">
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<begin loc="d,69,12,69,17">
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<display loc="d,71,7,71,13" displaytype="$write">
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<sformatf loc="d,71,7,71,13" name="*-* All Finished *-* " dtype_id="2"/>
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</display>
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<finish loc="d,72,7,72,14"/>
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</begin>
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</initial>
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</module>
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<package loc="a,0,0,0,0" name="$unit" origName="__024unit">
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<class loc="d,7,1,7,6" name="Packet" origName="Packet">
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<var loc="d,8,13,8,19" name="header" dtype_id="3" vartype="int" origName="header"/>
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<var loc="d,9,13,9,19" name="length" dtype_id="3" vartype="int" origName="length"/>
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<var loc="d,10,13,10,22" name="sublength" dtype_id="3" vartype="int" origName="sublength"/>
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<var loc="d,11,13,11,17" name="if_4" dtype_id="4" vartype="bit" origName="if_4"/>
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<var loc="d,12,13,12,20" name="iff_5_6" dtype_id="4" vartype="bit" origName="iff_5_6"/>
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<var loc="d,13,13,13,24" name="if_state_ok" dtype_id="4" vartype="bit" origName="if_state_ok"/>
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<var loc="d,15,13,15,18" name="array" dtype_id="5" vartype="" origName="array"/>
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<var loc="d,17,11,17,16" name="state" dtype_id="2" vartype="string" origName="state"/>
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<func loc="d,59,17,59,30" name="strings_equal" dtype_id="4">
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<var loc="d,59,17,59,30" name="strings_equal" dtype_id="4" dir="output" vartype="bit" origName="strings_equal"/>
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<var loc="d,59,38,59,39" name="a" dtype_id="2" dir="input" vartype="string" origName="a"/>
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<var loc="d,59,48,59,49" name="b" dtype_id="2" dir="input" vartype="string" origName="b"/>
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<assign loc="d,60,7,60,13" dtype_id="4">
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<eqn loc="d,60,16,60,18" dtype_id="6">
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<varref loc="d,60,14,60,15" name="a" dtype_id="2"/>
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<varref loc="d,60,19,60,20" name="b" dtype_id="2"/>
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</eqn>
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<varref loc="d,60,7,60,13" name="strings_equal" dtype_id="4"/>
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</assign>
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</func>
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<func loc="d,7,1,7,6" name="new" dtype_id="7">
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<stmtexpr loc="d,19,15,19,20">
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<taskref loc="d,19,15,19,20" name="empty_setup_constraint" dtype_id="7"/>
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</stmtexpr>
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<stmtexpr loc="d,21,15,21,19">
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<taskref loc="d,21,15,21,19" name="size_setup_constraint" dtype_id="7"/>
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</stmtexpr>
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<stmtexpr loc="d,28,15,28,18">
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<taskref loc="d,28,15,28,18" name="ifs_setup_constraint" dtype_id="7"/>
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</stmtexpr>
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<stmtexpr loc="d,39,15,39,23">
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<taskref loc="d,39,15,39,23" name="arr_uniq_setup_constraint" dtype_id="7"/>
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</stmtexpr>
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<stmtexpr loc="d,46,15,46,20">
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<taskref loc="d,46,15,46,20" name="order_setup_constraint" dtype_id="7"/>
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</stmtexpr>
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<stmtexpr loc="d,48,15,48,18">
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<taskref loc="d,48,15,48,18" name="dis_setup_constraint" dtype_id="7"/>
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</stmtexpr>
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<stmtexpr loc="d,54,15,54,19">
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<taskref loc="d,54,15,54,19" name="meth_setup_constraint" dtype_id="7"/>
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</stmtexpr>
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</func>
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<task loc="d,7,1,7,6" name="empty_setup_constraint"/>
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<var loc="d,19,15,19,20" name="constraint" dtype_id="8" vartype="VlRandomizer" origName="constraint"/>
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<task loc="d,7,1,7,6" name="size_setup_constraint">
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<stmtexpr loc="d,8,13,8,19">
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<cmethodhard loc="d,8,13,8,19" name="write_var" dtype_id="7">
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<varref loc="d,8,13,8,19" name="constraint" dtype_id="8"/>
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<varref loc="d,8,13,8,19" name="header" dtype_id="3"/>
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<const loc="d,8,9,8,12" name="64'h20" dtype_id="9"/>
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<cexpr loc="d,8,13,8,19" dtype_id="3">
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<text loc="d,8,13,8,19"/>
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</cexpr>
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</cmethodhard>
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</stmtexpr>
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<stmtexpr loc="d,22,18,22,20">
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<cmethodhard loc="d,22,18,22,20" name="hard" dtype_id="7">
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<varref loc="d,22,18,22,20" name="constraint" dtype_id="8"/>
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<const loc="d,22,18,22,20" name=""(and (bvsgt header #x00000000) (bvsle header #x00000007))"" dtype_id="2"/>
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</cmethodhard>
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</stmtexpr>
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<stmtexpr loc="d,9,13,9,19">
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<cmethodhard loc="d,9,13,9,19" name="write_var" dtype_id="7">
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<varref loc="d,9,13,9,19" name="constraint" dtype_id="8"/>
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<varref loc="d,9,13,9,19" name="length" dtype_id="3"/>
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<const loc="d,8,9,8,12" name="64'h20" dtype_id="9"/>
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<cexpr loc="d,9,13,9,19" dtype_id="3">
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<text loc="d,9,13,9,19"/>
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</cexpr>
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</cmethodhard>
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</stmtexpr>
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<stmtexpr loc="d,23,14,23,16">
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<cmethodhard loc="d,23,14,23,16" name="hard" dtype_id="7">
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<varref loc="d,23,14,23,16" name="constraint" dtype_id="8"/>
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<const loc="d,23,14,23,16" name=""(bvsle length #x0000000f)"" dtype_id="2"/>
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</cmethodhard>
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</stmtexpr>
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<stmtexpr loc="d,24,14,24,16">
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<cmethodhard loc="d,24,14,24,16" name="hard" dtype_id="7">
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<varref loc="d,24,14,24,16" name="constraint" dtype_id="8"/>
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<const loc="d,24,14,24,16" name=""(bvsge length header)"" dtype_id="2"/>
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</cmethodhard>
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</stmtexpr>
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<stmtexpr loc="d,25,7,25,13">
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<cmethodhard loc="d,25,7,25,13" name="hard" dtype_id="7">
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<varref loc="d,25,7,25,13" name="constraint" dtype_id="8"/>
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<const loc="d,25,7,25,13" name=""length"" dtype_id="2"/>
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</cmethodhard>
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</stmtexpr>
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</task>
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<task loc="d,7,1,7,6" name="ifs_setup_constraint"/>
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<task loc="d,7,1,7,6" name="arr_uniq_setup_constraint"/>
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<task loc="d,7,1,7,6" name="order_setup_constraint"/>
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<task loc="d,7,1,7,6" name="dis_setup_constraint">
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<stmtexpr loc="d,10,13,10,22">
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<cmethodhard loc="d,10,13,10,22" name="write_var" dtype_id="7">
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<varref loc="d,10,13,10,22" name="constraint" dtype_id="8"/>
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<varref loc="d,10,13,10,22" name="sublength" dtype_id="3"/>
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<const loc="d,8,9,8,12" name="64'h20" dtype_id="9"/>
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<cexpr loc="d,10,13,10,22" dtype_id="3">
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<text loc="d,10,13,10,22"/>
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</cexpr>
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</cmethodhard>
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</stmtexpr>
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<stmtexpr loc="d,49,7,49,11">
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<cmethodhard loc="d,49,7,49,11" name="hard" dtype_id="7">
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<varref loc="d,49,7,49,11" name="constraint" dtype_id="8"/>
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<const loc="d,49,12,49,21" name=""sublength"" dtype_id="2"/>
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</cmethodhard>
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</stmtexpr>
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<stmtexpr loc="d,50,7,50,14">
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<cmethodhard loc="d,50,7,50,14" name="hard" dtype_id="7">
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<varref loc="d,50,7,50,14" name="constraint" dtype_id="8"/>
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<const loc="d,50,20,50,29" name=""sublength"" dtype_id="2"/>
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</cmethodhard>
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</stmtexpr>
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<stmtexpr loc="d,51,17,51,19">
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<cmethodhard loc="d,51,17,51,19" name="hard" dtype_id="7">
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<varref loc="d,51,17,51,19" name="constraint" dtype_id="8"/>
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<const loc="d,51,17,51,19" name=""(bvsle sublength length)"" dtype_id="2"/>
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</cmethodhard>
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</stmtexpr>
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</task>
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<task loc="d,7,1,7,6" name="meth_setup_constraint"/>
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</class>
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</package>
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<typetable loc="a,0,0,0,0">
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<basicdtype loc="d,22,14,22,15" id="6" name="logic"/>
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<basicdtype loc="d,25,21,25,22" id="10" name="logic" left="31" right="0"/>
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<basicdtype loc="d,71,7,71,13" id="2" name="string"/>
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<basicdtype loc="d,8,9,8,12" id="3" name="int" left="31" right="0" signed="true"/>
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<basicdtype loc="d,11,9,11,12" id="4" name="bit"/>
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<unpackarraydtype loc="d,15,18,15,19" id="5" sub_dtype_id="3">
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<range loc="d,15,18,15,19">
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<const loc="d,15,19,15,20" name="32'h0" dtype_id="10"/>
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<const loc="d,15,19,15,20" name="32'h1" dtype_id="10"/>
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</range>
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</unpackarraydtype>
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<voiddtype loc="d,7,1,7,6" id="7"/>
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<classrefdtype loc="d,67,4,67,10" id="1" name="Packet"/>
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<basicdtype loc="d,7,1,7,6" id="8" name="VlRandomizer"/>
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<basicdtype loc="d,8,9,8,12" id="9" name="logic" left="63" right="0"/>
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</typetable>
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</netlist>
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</verilator_xml>
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