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65 lines
1.9 KiB
Systemverilog
65 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Packet;
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rand int m_one;
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constraint cons { m_one > 0 && m_one < 2; }
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Packet other;
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task test1;
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// TODO Verilator ignores this setting currently, always returning 0 (constraint off)
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cons.constraint_mode(1);
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cons.constraint_mode(0);
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if (cons.constraint_mode() != 0) $stop;
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endtask
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endclass
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module t (/*AUTOARG*/);
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Packet p;
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int v;
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initial begin
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p = new;
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v = p.randomize();
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if (v != 1) $stop;
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if (p.m_one != 1) $stop;
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// IEEE: function void object[.constraint_identifier].constraint_mode(bit on_off);
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// IEEE: function int object.constraint_identifier.constraint_mode();
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// TODO Verilator ignores this setting currently, always returning 1 (rand on)
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// TODO test that these control constraints as specified
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p.constraint_mode(0);
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p.constraint_mode(1);
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// Not legal to get current constraint_mode() value on a class-only call
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// TODO Verilator ignores this setting currently, always returning 0 (constraint off)
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// TODO test that these control constraints as specified
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p.cons.constraint_mode(1);
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p.cons.constraint_mode(0);
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if (p.cons.constraint_mode() != 0) $stop;
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// TODO Verilator ignores this setting currently, always returning 0 (constraint off)
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// TODO test that these control constraints as specified
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p.other = new;
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p.other.cons.constraint_mode(1);
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p.other.cons.constraint_mode(0);
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if (p.other.cons.constraint_mode() != 0) $stop;
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p.test1();
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// TODO for example way to test this, see t_randomize_rand_mode.v
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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