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23 lines
446 B
Systemverilog
23 lines
446 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t(
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output wire res
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);
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function automatic logic foo(logic bar);
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foo = '0;
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endfunction
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logic a, b;
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logic [0:0][1:0] array;
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assign b = 0;
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assign a = foo(b);
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assign res = array[a][a];
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endmodule
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