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546 lines
17 KiB
Systemverilog
546 lines
17 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 Yutetsu TAKATSUKASA.
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// SPDX-License-Identifier: CC0-1.0
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// This function always returns 0, so safe to take bitwise OR with any value.
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// Calling this function stops constant folding as Verialtor does not know
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// what this function returns.
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import "DPI-C" context function int c_fake_dependency();
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [31:0] in = crc[31:0];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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logic o; // From test of Test.v
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// End of automatics
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wire [31:0] i = crc[31:0];
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Test test(/*AUTOINST*/
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// Outputs
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.o (o),
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// Inputs
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.clk (clk),
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.i (i[31:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {63'b0, o};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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$display("o %b", o);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc < 10) begin
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sum <= '0;
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end
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else if (cyc < 99) begin
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end
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else begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h4c5aa8d19cd13750
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test(/*AUTOARG*/
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// Outputs
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o,
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// Inputs
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clk, i
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);
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input clk;
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input [31:0] i;
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logic [31:0] d;
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logic d0, d1, d2, d3, d4, d5, d6, d7;
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logic bug3182_out;
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logic bug3197_out;
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logic bug3445_out;
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logic bug3470_out;
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logic bug3509_out;
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wire bug3399_out0;
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wire bug3399_out1;
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logic bug3786_out;
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logic bug3824_out;
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logic bug4059_out;
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logic bug4832_out;
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logic bug4837_out;
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logic bug4857_out;
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logic bug4864_out;
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output logic o;
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logic [18:0] tmp;
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assign o = ^tmp;
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always_ff @(posedge clk) begin
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d <= i;
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d0 <= i[0];
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d1 <= i[1];
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d2 <= i[2];
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d3 <= i[3];
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d4 <= i[4];
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d5 <= i[5];
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d6 <= i[6];
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d7 <= i[7];
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end
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always_ff @(posedge clk) begin
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// Cover more lines in V3Const.cpp
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tmp[0] <= (d0 || (!d0 && d1)) ^ ((!d2 && d3) || d2); // maatchOrAndNot()
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tmp[1] <= ((32'd2 ** i) & 32'h10) == 32'b0; // replacePowShift
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tmp[2] <= ((d0 & d1) | (d0 & d2))^ ((d3 & d4) | (d5 & d4)); // replaceAndOr()
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tmp[3] <= d0 <-> d1; // replaceLogEq()
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tmp[4] <= i[0] & (i[1] & (i[2] & (i[3] | d[4]))); // ConstBitOpTreeVisitor::m_frozenNodes
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tmp[5] <= bug3182_out;
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tmp[6] <= bug3197_out;
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tmp[7] <= bug3445_out;
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tmp[8] <= bug3470_out;
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tmp[9] <= bug3509_out;
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tmp[10]<= bug3399_out0;
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tmp[11]<= bug3399_out1;
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tmp[12]<= bug3786_out;
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tmp[13]<= bug3824_out;
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tmp[14]<= bug4059_out;
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tmp[15]<= bug4832_out;
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tmp[16]<= bug4837_out;
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tmp[17]<= bug4857_out;
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tmp[18]<= bug4864_out;
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end
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bug3182 i_bug3182(.in(d[4:0]), .out(bug3182_out));
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bug3197 i_bug3197(.clk(clk), .in(d), .out(bug3197_out));
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bug3445 i_bug3445(.clk(clk), .in(d), .out(bug3445_out));
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bug3470 i_bug3470(.clk(clk), .in(d), .out(bug3470_out));
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bug3509 i_bug3509(.clk(clk), .in(d), .out(bug3509_out));
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bug3399 i_bug3399(.clk(clk), .in(d), .out0(bug3399_out0), .out1(bug3399_out1));
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bug3786 i_bug3786(.clk(clk), .in(d), .out(bug3786_out));
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bug3824 i_bug3824(.clk(clk), .in(d), .out(bug3824_out));
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bug4059 i_bug4059(.clk(clk), .in(d), .out(bug4059_out));
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bug4832 i_bug4832(.clk(clk), .in(d), .out(bug4832_out));
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bug4837 i_bug4837(.clk(clk), .in(d), .out(bug4837_out));
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bug4857 i_bug4857(.clk(clk), .in(d), .out(bug4857_out));
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bug4864 i_bug4864(.clk(clk), .in(d), .out(bug4864_out));
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endmodule
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module bug3182(in, out);
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input wire [4:0] in;
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output wire out;
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logic [4:0] bit_source;
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/* verilator lint_off WIDTH */
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always @(in)
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bit_source = c_fake_dependency() | in;
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wire [5:0] tmp = bit_source; // V3Gate should inline this
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assign out = ~(tmp >> 5) & (bit_source == 5'd10);
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/* verilator lint_on WIDTH */
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endmodule
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module bug3197(input wire clk, input wire [31:0] in, output out);
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logic [63:0] d;
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always_ff @(posedge clk)
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d <= {d[31:0], in[0] ? in : 32'b0};
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wire tmp0 = (|d[38:0]);
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assign out = (d[39] | tmp0);
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endmodule
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// See issue #3445
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// An unoptimized node is kept as frozen node, but its LSB and polarity were not saved.
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// AST of RHS of result0 looks as below:
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// AND(SHIFTR(AND(WORDSEL(ARRAYSEL(VARREF)), WORDSEL(ARRAYSEL(VARREF)))), 32'd11)
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// ~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~
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// Two of WORDSELs are frozen nodes. They are under SHIFTR of 11 bits.
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//
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// Fixing issue #3445 needs to
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// 1. Take AstShiftR and AstNot into op count when diciding optimizable or not
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// (result0 and result2 in the test)
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// 2. Insert AstShiftR if LSB of the frozen node is not 0 (result1 in the test)
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// 3. Insert AstNot if polarity of the frozen node is false (resutl3 in the
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// test)
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module bug3445(input wire clk, input wire [31:0] in, output wire out);
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logic [127:0] d;
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always_ff @(posedge clk)
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d <= {d[95:0], in};
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typedef struct packed {
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logic a;
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logic [ 2:0] b;
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logic [ 2:0] c;
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logic [ 1:0] d;
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logic [ 7:0] e;
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logic [31:0] f;
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logic [ 3:0] g;
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logic [31:0] h;
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logic i;
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logic [41:0] j;
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} packed_struct;
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packed_struct st[4];
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// This is always 1'b0, but Verilator cannot notice it.
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// This signal helps to reveal wrong optimization of result2 and result3.
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logic zero;
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always_ff @(posedge clk) begin
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st[0] <= d;
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st[1] <= st[0];
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st[2] <= st[1];
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st[3] <= st[2];
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zero <= c_fake_dependency() > 0;
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end
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logic result0, result1, result2, result3;
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always_ff @(posedge clk) begin
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// Cannot optimize further.
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result0 <= (st[0].g[0] & st[0].h[0]) & (in[0] == 1'b0);
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// There are redundant !in[0] terms. They should be simplified.
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result1 <= (!in[0] & (st[1].g[0] & st[1].h[0])) & ((in[0] == 1'b0) & !in[0]);
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// Cannot optimize further.
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result2 <= !(st[2].g[0] & st[2].h[0]) & (zero == 1'b0);
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// There are redundant zero terms. They should be simplified.
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result3 <= (!zero & !(st[3].g[0] & st[3].h[0])) & ((zero == 1'b0) & !zero);
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end
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assign out = result0 ^ result1 ^ (result2 | result3);
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endmodule
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// Bug3470
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// CCast had been ignored in bit op tree optimization
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// Assume the following HDL input:
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// (^d[38:32]) ^ (^d[31:0])
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// where d is logic [38:0]
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// ^d[31:0] becomes REDXOR(CCast(uint32_t, d)),
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// but CCast was ignored and interpreted as ^d[38:0].
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// Finally (^d[38:32]) ^ (^d31:0]) was wrongly transformed to
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// (^d[38:32]) ^ (^d[38:0])
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// -> (^d[38:32]) ^ ((^d[38:32]) ^ (^d[31:0]))
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// -> ^d[31:0]
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// Of course the correct result is ^d[38:0] = ^d
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module bug3470(input wire clk, input wire [31:0] in, output wire out);
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logic [38:0] d;
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always_ff @(posedge clk)
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d <= {d[6:0], in};
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logic tmp, expected;
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always_ff @(posedge clk) begin
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tmp <= ^(d >> 32) ^ (^d[31:0]);
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expected <= ^d;
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end
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always @(posedge clk)
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if (tmp != expected) $stop;
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assign out = tmp;
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endmodule
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// Bug3509
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// Only bit range of "var" was considered in
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// "comp == (mask & var)"
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// and
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// "comp != (mask & var)"
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//
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// It caused wrong result if "comp" has wider bit width because
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// upper bit of "comp" was ignored.
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//
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// If "comp" has '1' in upper bit range than "var",
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// the result is constant after optimization.
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module bug3509(input wire clk, input wire [31:0] in, output reg out);
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reg [2:0] r0;
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always_ff @(posedge clk)
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r0 <= in[2:0];
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wire [3:0] w1_0 = {1'b0, in[2:0]};
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wire [3:0] w1_1 = {1'b0, r0};
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wire tmp[4];
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// tmp[0:1] is always 0 because w1[3] == 1'b0
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// tmp[2:3] is always 1 because w1[3] == 1'b0
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assign tmp[0] = w1_0[3:2] == 2'h2 && w1_0[1:0] != 2'd3;
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assign tmp[1] = w1_1[3:2] == 2'h2 && w1_1[1:0] != 2'd3;
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assign tmp[2] = w1_0[3:2] != 2'h2 || w1_0[1:0] == 2'd3;
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assign tmp[3] = w1_1[3:2] != 2'h2 || w1_1[1:0] == 2'd3;
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always_ff @(posedge clk) begin
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out <= tmp[0] | tmp[1] | !tmp[2] | !tmp[3];
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end
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always @(posedge clk) begin
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if(tmp[0]) begin
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$display("tmp[0] != 0");
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$stop;
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end
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if(tmp[1]) begin
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$display("tmp[1] != 0");
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$stop;
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end
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if(!tmp[2]) begin
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$display("tmp[2] != 1");
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$stop;
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end
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if(!tmp[3]) begin
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$display("tmp[3] != 1");
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$stop;
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end
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end
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endmodule
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// Bug3399
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// replaceShiftSame() in V3Const.cpp optimizes
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// Or(Shift(ll,CONSTlr),Shift(rl,CONSTrr==lr)) -> Shift(Or(ll,rl),CONSTlr)
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// (Or/And may also be reversed)
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//
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// dtype of Or after the transformation must be as same as ll and rl, but was dtype of Or BEFORE transformation.
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// When the result of Shift was 1 bit width, bit op tree optimization
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// optimized the tree even though the graph needs more width.
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// Remember that the target of bit op tree optimization is 1 bit width.
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module bug3399(input wire clk, input wire [31:0] in, inout wire out0, inout wire out1);
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logic [1:0] driver = '0;
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logic [1:0] d;
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always_ff @(posedge clk) begin
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driver <= 2'b11;
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d <= in[1:0];
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end
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assign out0 = driver[0] ? d[0] : 1'bz;
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assign out1 = driver[1] ? d[1] : 1'bz;
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endmodule
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// Bug3786
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// When V3Expand is skipped, wide number is not split by WORDSEL.
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// Bit op tree opt. expects that bit width is 64 bit at most.
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module bug3786(input wire clk, input wire [31:0] in, inout wire out);
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logic [127:0] d0, d1;
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always_ff @(posedge clk) begin
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d0 <= {d0[127:32], in};
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d1 <= d1;
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end
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assign out = ^{d1, d0};
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endmodule
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// Bug3824
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// When a variable is shift-out, the term becomes 0.
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// Such behavior was not considered in Or-tree.
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module bug3824(input wire clk, input wire [31:0] in, output wire out);
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logic [5:0] a;
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always_ff @(posedge clk) a <= in[5:0];
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logic [6:0] b;
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assign b = {1'b0, a};
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logic c_and;
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assign c_and = (b[6]); // c_and is always 1'b0
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always_comb if (c_and != 1'b0) $stop;
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logic d_and;
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always_ff @(posedge clk) d_and <= (&a) & c_and;
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logic c_or;
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assign c_or = ~(b[6]); // c_or is always 1'b1 as b[6] is 1'b0
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always_comb if (c_or != 1'b1) $stop;
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logic d_or;
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always_ff @(posedge clk) d_or <= (|a) | c_or;
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logic c_xor;
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assign c_xor = ^(b[6]); // c_xor is always 1'b0
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always_comb if (c_xor != 1'b0) $stop;
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logic d_xor;
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always_ff @(posedge clk) d_xor <= (^a) ^ c_xor;
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assign out = d_and ^ d_or ^ d_xor;
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endmodule
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/// See issue #4059
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// Frozen node in an xor tree held unnecessary poloarity.
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// In an XOR tree, the entire result is flipped if necessary according to
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// total polarity. This bug was introduced when fixing issue #3445.
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module bug4059(input wire clk, input wire [31:0] in, output wire out);
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wire [127:0] words_i;
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for (genvar i = 0; i < $bits(in); ++i) begin
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always_ff @(posedge clk)
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words_i[4 * i +: 4] <= {4{in[i]}};
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end
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wire _000_ = ~(words_i[104] ^ words_i[96]);
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wire _001_ = ~(words_i[88] ^ words_i[80]);
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wire _002_ = ~(_000_ ^ _001_);
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wire _003_ = words_i[72] ^ words_i[64];
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wire _004_ = words_i[120] ^ words_i[112];
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wire _005_ = ~(_003_ ^ _004_);
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wire _006_ = ~(_002_ ^ _005_);
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wire _007_ = words_i[40] ^ words_i[32];
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wire _008_ = ~(words_i[24] ^ words_i[16]);
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wire _009_ = ~(_007_ ^ _008_);
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wire _010_ = words_i[8] ^ words_i[0];
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wire _011_ = words_i[56] ^ words_i[48];
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wire _012_ = ~(_010_ ^ _011_);
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wire _013_ = ~(_009_ ^ _012_);
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assign out = ~(_006_ ^ _013_);
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endmodule
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/// See issue #4832
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// !(d[32 + 3] & in[3]) & d[32 + 22]
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// was wrongly transformed to
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// !d[32 + 3] & d[32 + 22] & !in[3]
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// A subtree under NOT should be untouched, but was not.
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// Testing OR subtree too.
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module bug4832(input wire clk, input wire [31:0] in, output out);
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logic [95:0] d;
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always_ff @(posedge clk)
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d <= {d[63:0], in};
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logic [31:0] tmp_and;
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logic [31:0] tmp_or;
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logic result_and;
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logic result_or;
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assign tmp_and = (d[63:32] & in) >> 3;
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assign tmp_or = (d[63:32] | in) >> 8;
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always_ff @(posedge clk) begin
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result_and <= !tmp_and[0] & d[32 + 22];
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result_or <= !tmp_or[0] | d[32 + 21];
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end
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assign out = result_and ^ result_or;
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endmodule
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/// See issue #4837 and $4841
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// replaceShiftOp() in V3Const did not update widthMin, then bit-op-tree opt.
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// was wrongly triggered for the subtree.
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// replaceShiftOp() transforms as below:
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// SHIFT(AND(a,b),CONST)->AND(SHIFT(a,CONST),SHIFT(b,CONST))
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// AND after the transformation must have same minWidth as the original SHIFT
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// e.g. SHIFTL(AND(a, b), 1) => AND(SHIFTL(a, 1), SHIFTL(b, 1))
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// AND in the result must have 1 bit larger widthMin than the original AND
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module bug4837(input wire clk, input wire [31:0] in, output out);
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logic [95:0] d;
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always_ff @(posedge clk)
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d <= {d[63:0], in};
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wire celloutsig_0z;
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wire [1:0] celloutsig_1z;
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wire celloutsig_2z;
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wire [95:0] out_data;
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assign celloutsig_0z = d[83] < d[74];
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assign celloutsig_1z = { d[54], celloutsig_0z } & { d[42], celloutsig_0z };
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assign celloutsig_2z = d[65:64] < d[83:82];
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assign { out_data[33:32], out_data[0] } = { celloutsig_1z, celloutsig_2z };
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assign out = out_data[33] ^ out_data[32] ^ out_data[0];
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endmodule
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// See issue #4857
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// (1'b0 != (!a)) | b was wrongly optimized to
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// (a | b) & 1'b1
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// polarity was not considered when traversing NEQ under AND/OR tree
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module bug4857(input wire clk, input wire [31:0] in, output out);
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logic [95:0] d;
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always_ff @(posedge clk)
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d <= {d[63:0], in};
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wire celloutsig_12z;
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wire celloutsig_15z;
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wire celloutsig_17z;
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wire celloutsig_4z;
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wire celloutsig_67z;
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wire celloutsig_9z;
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logic [95:0] in_data;
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logic result;
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// verilator lint_off UNDRIVEN
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wire [95:0] out_data;
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// verilator lint_on UNDRIVEN
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assign celloutsig_4z = ~(in_data[72] & in_data[43]); // 1
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assign celloutsig_67z = | { in_data[64], celloutsig_12z }; // 0
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assign celloutsig_15z = in_data[43] & ~(celloutsig_4z); // 0
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assign celloutsig_9z = celloutsig_17z & ~(in_data[43]); // 00000000
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assign celloutsig_17z = celloutsig_15z & ~(in_data[43]);// 0
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assign celloutsig_12z = celloutsig_4z != celloutsig_9z; // 1
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assign out_data[32] = celloutsig_67z; // 1
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assign in_data = d;
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always_ff @ (posedge clk)
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result <= out_data[32];
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assign out = result;
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endmodule
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|
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|
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// See issue #4864
|
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// (((in_data[32*1] & 32'h3000000 != 0) | (in_data[32*2 + 25])| (sig_b != 9'b0)) >> 4) | sig_b[2]
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// was wrongly optimized as below.
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// ((in_data[32] & 32'h30000000) != 0 >> 0) | (in_data[32*2 + 29])|((sig_b & 9'h1f4) != 0)
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|
// The result of EQ/NE is just 1 bit width, so EQ/NE under SHFITR cannot be treated as a multi-bit term
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|
// such as AND/OR.
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|
module bug4864(input wire clk, input wire [31:0] in, output wire out);
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logic [159:0] clkin_data = '0;
|
|
logic [95:0] in_data = '0;
|
|
int cycle = 0;
|
|
always @(posedge clk) begin
|
|
if (in[0]) begin
|
|
cycle <= cycle + 1;
|
|
if (cycle == 0) begin
|
|
clkin_data <= 160'hFFFFFFFF_00000000_00000000_00000000_00000000;
|
|
end else if (cycle == 1) begin
|
|
in_data <= 96'h00000000_FFFFFFFF_00000000;
|
|
end else begin
|
|
clkin_data <= 160'hFFFFFFFF_00000000_00000000_00000000_FFFFFFFF;
|
|
end
|
|
end
|
|
end
|
|
|
|
wire moveme;
|
|
wire sig_a;
|
|
reg [8:0] sig_b;
|
|
wire sig_c;
|
|
wire [20:0] sig_d;
|
|
reg sig_e;
|
|
|
|
logic myfirst, mysecond;
|
|
assign myfirst = 1'b0;
|
|
assign mysecond = 1'b0;
|
|
|
|
always_ff @(posedge clkin_data[0], posedge myfirst, posedge mysecond)
|
|
if (myfirst) sig_e <= 1'b0;
|
|
else if (mysecond) sig_e <= 1'b1;
|
|
else if (clkin_data[128]) sig_e <= sig_d[7];
|
|
|
|
always_ff @(posedge clkin_data[128])
|
|
sig_b <= '0;
|
|
|
|
assign sig_a = in_data[89]; // 1'b0;
|
|
assign sig_c = | { in_data[61:60], sig_b, sig_a };
|
|
assign sig_d = ~ { moveme, 6'b0, sig_b, 1'b0, sig_c, 3'b0 };
|
|
assign moveme = 1'b1;
|
|
|
|
assign out = sig_e;
|
|
endmodule
|