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25 lines
506 B
Systemverilog
25 lines
506 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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typedef enum {efgh} en;
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module t (/*AUTOARG*/);
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initial begin
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en e;
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string s;
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s = {"a", "b"};
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if (s != "ab") $stop;
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e = efgh;
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s = {"abcd", e.name(), "ijkl"};
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if (s != "abcdefghijkl") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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