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85 lines
1.5 KiB
Systemverilog
85 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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virtual class VBase;
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virtual function int hello;
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return 1;
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endfunction
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endclass
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class VA extends VBase;
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virtual function int hello;
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return 2;
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endfunction
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endclass
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class VB extends VBase;
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virtual function int hello;
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return 3;
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endfunction
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endclass
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virtual class uvm_phase;
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virtual function int exec_func;
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return 0;
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endfunction
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endclass
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class uvm_topdown_phase extends uvm_phase;
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function int get1;
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return exec_func();
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endfunction
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endclass
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class uvm_build_phase extends uvm_topdown_phase;
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virtual function int exec_func;
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return 1;
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endfunction
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endclass
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virtual class Cls;
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uvm_phase ph;
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endclass
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class ExtendsCls extends Cls;
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function new;
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uvm_build_phase bp = new;
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ph = bp;
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endfunction
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function int get1;
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return super.ph.exec_func();
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endfunction
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endclass
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module t;
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initial begin
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VA va = new;
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VB vb = new;
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VBase b;
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uvm_build_phase ph;
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ExtendsCls ec;
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if (va.hello() != 2) $stop;
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if (vb.hello() != 3) $stop;
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b = va;
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if (b.hello() != 2) $stop;
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b = vb;
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if (b.hello() != 3) $stop;
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ph = new;
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if (ph.get1() != 1) $stop;
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ec = new;
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if (ec.get1() != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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