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25 lines
666 B
Systemverilog
25 lines
666 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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typedef enum bit {A = 0, B = 1} enum_t;
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class Converter #(type T);
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function int toInt(T t);
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return int'(t);
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endfunction
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endclass
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module t;
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initial begin
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Converter#(enum_t) conv1 = new;
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// enum types does not match with other types (IEEE 1800-2023 6.22.1 and 6.22.4)
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// The assignment and the function call should throw an error.
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Converter#(bit) conv2 = conv1;
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conv1.toInt(0);
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$stop;
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end
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endmodule
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