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40 lines
969 B
Systemverilog
40 lines
969 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class u_object;
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string m_name;
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function new(string name);
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m_name = name;
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endfunction
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endclass
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class u_cache#(type KEY_T=int, type DATA_T=int) extends u_object;
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typedef int unsigned size_t;
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int m_max_size;
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extern function new(string name="u_cache", size_t max_size = 256);
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endclass
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// #() not required below, see IEEE 1800-2023 8.25.1
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function u_cache::new(string name="u_cache", u_cache::size_t max_size = 256);
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super.new(name);
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this.m_max_size = max_size;
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endfunction
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module t(/*AUTOARG*/);
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u_cache #(real, real) obj;
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initial begin
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obj = new("fred", 62);
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if (obj.m_name != "fred") $stop;
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if (obj.m_max_size != 62) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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