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79 lines
1.6 KiB
Systemverilog
79 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class ClsNoArg;
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const int imembera; // Ok for new() to assign to a const
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function new();
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int other = other_func();
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imembera = 5;
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if (other != 6) $stop;
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endfunction : new
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function int other_func();
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return 6;
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endfunction
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endclass
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class ClsArg;
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int imembera;
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function new(int i);
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imembera = i + 1;
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endfunction
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function int geta;
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return imembera;
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endfunction
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static function ClsArg create6;
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ClsArg obj;
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obj = new(6 - 1);
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return obj;
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endfunction
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endclass
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class Cls2Arg;
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int imembera;
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int imemberb;
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function new(int i, int j);
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imembera = i + 1;
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imemberb = j + 2;
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endfunction
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function Cls2Arg clone();
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Cls2Arg ret;
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ret = new(imembera, imemberb);
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return ret;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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ClsNoArg c1;
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ClsArg c2;
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Cls2Arg c3;
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Cls2Arg c4;
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c1 = new;
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if (c1.imembera != 5) $stop;
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c2 = new(3 - 1);
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if (c2.imembera != 3) $stop;
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if (c2.geta() != 3) $stop;
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c2 = ClsArg::create6();
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if (c2.imembera != 6) $stop;
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if (c2.geta() != 6) $stop;
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c3 = new(4, 5);
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if (c3.imembera != 5) $stop;
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if (c3.imemberb != 7) $stop;
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c4 = c3.clone();
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if (c4.imembera != 6) $stop;
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if (c4.imemberb != 9) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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