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46 lines
1.0 KiB
Systemverilog
46 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Anthony Donlon.
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// SPDX-License-Identifier: CC0-1.0
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/// Test for bug4553
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// bit0: 'new' called
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// bit1: 'myfunc' called
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// bit2: 'myfunc' in class called
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int calls = 0;
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module t;
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// int calls = 0; // TODO: Error: Internal Error: Can't locate varref scope
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function void myfunc();
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calls |= 32'b10;
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endfunction : myfunc
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class Cls #(int A = 0);
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function new();
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calls |= 32'b1;
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endfunction : new
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function void myfunc();
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calls |= 32'b100;
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endfunction : myfunc
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endclass
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Cls #(100) cls;
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// this block is following the definition of Cls
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initial begin
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cls = new;
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myfunc();
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if (calls != 32'b011) begin
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$write("calls: %0b\n", calls);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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