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35 lines
709 B
Systemverilog
35 lines
709 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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typedef struct packed {
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int x;
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int y;
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int z;
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} my_struct;
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class Cls;
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function my_struct get_struct;
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my_struct s;
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s.x = 1;
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s.y = 2;
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s.z = 3;
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return s;
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endfunction
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endclass : Cls
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module t (/*AUTOARG*/);
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initial begin
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Cls c = new;
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my_struct s = c.get_struct;
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if (s.x != 1) $stop;
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if (s.y != 2) $stop;
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if (s.z != 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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