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38 lines
823 B
Systemverilog
38 lines
823 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Base #(type T = integer);
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T m_count;
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function void test1();
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if (this.m_count != 0) $stop;
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if (this.m_count++ != 0) $stop;
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if (this.m_count != 1) $stop;
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if (m_count++ != 1) $stop;
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if (this.m_count != 2) $stop;
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endfunction
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endclass
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class Cls #(type T = integer) extends Base #(T);
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endclass
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module t;
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Cls #(int) c;
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initial begin
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c = new;
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c.test1();
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c.m_count = 0;
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if (c.m_count != 0) $stop;
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if (c.m_count++ != 0) $stop;
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if (c.m_count != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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