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48 lines
1.1 KiB
Systemverilog
48 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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interface class Courier;
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pure virtual function void deliver();
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endclass
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class Person implements Courier;
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virtual function void deliver();
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$display("slow delivery");
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endfunction
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endclass
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interface class Seats;
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pure virtual function int seats();
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endclass
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class Vehicle;
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endclass
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class Car extends Vehicle implements Courier, Seats;
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virtual function void deliver();
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$display("fast delivery");
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endfunction
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virtual function int seats(); return 4; endfunction
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endclass
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class MetaCar extends Car;
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endclass
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function void do_delivery(Courier courier);
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courier.deliver();
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endfunction
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initial begin
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MetaCar car;
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car = new();
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do_delivery(car);
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if (car.seats() != 4) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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