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48 lines
1.2 KiB
Systemverilog
48 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package Pkg;
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class Base0;
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int baseonly;
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int baseover;
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function void b_set_bo(int v); baseover = v; endfunction
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function int b_get_bo(); return baseover; endfunction
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function int get_bo(); return baseover; endfunction
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endclass
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endpackage
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class Ext extends Pkg::Base0;
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int baseover;
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int extonly;
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function void e_set_bo(int v); baseover = v; endfunction
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function int e_get_bo(); return baseover; endfunction
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function int get_bo(); return baseover; endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Ext c;
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c = new;
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c.baseonly = 10;
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c.baseover = 20;
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c.extonly = 30;
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if (c.baseonly != 10) $stop;
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if (c.baseover != 20) $stop;
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if (c.extonly != 30) $stop;
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c.b_set_bo(100);
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c.e_set_bo(200);
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if (c.b_get_bo() != 100) $stop;
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if (c.e_get_bo() != 200) $stop;
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if (c.get_bo() != 200) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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