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37 lines
802 B
Systemverilog
37 lines
802 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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class Cls;
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bit x = 1;
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endclass
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module t (/*AUTOARG*/);
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Cls obj1;
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Cls obj2;
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initial begin
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obj1 = new;
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`checkh(obj1.x, 1);
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obj1.x = 0;
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obj2 = new obj1;
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`checkh(obj2.x, 0);
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obj2.x = 1;
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`checkh(obj1.x, 0);
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`checkh(obj2.x, 1);
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obj2.x = 0;
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`checkh(obj2.x, 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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