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37 lines
1.1 KiB
Systemverilog
37 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Check == and != operations performed on class objects
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Ilya Barkov.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end
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// Two checks because == and != may not be derived from each other
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`define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0)
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`define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1)
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class Cls;
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int i;
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endclass
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class ExtendCls extends Cls;
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endclass
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module t;
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initial begin
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Cls a = new;
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Cls b = new;
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ExtendCls ext = new;
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`check_ne(a, b)
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`check_ne(a, ext)
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`check_ne(ext, a)
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a = b;
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`check_eq(a, b)
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a = ext;
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`check_eq(a, ext)
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`check_eq(ext, a)
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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