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28 lines
534 B
Systemverilog
28 lines
534 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Cls1;
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endclass
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class Cls2;
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endclass
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class ExtCls1;
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endclass
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module t (/*AUTOARG*/);
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Cls1 c1;
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Cls2 c2;
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ExtCls1 ext_c1;
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initial begin
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c1 = (c1 != null) ? c1 : c2;
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c1 = (c1 != null) ? c2 : c2;
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c2 = (c1 == null) ? 1'b1 : c2;
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ext_c1 = (c1 == null) ? ext_c1 : c1;
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end
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endmodule
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