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45 lines
966 B
Systemverilog
45 lines
966 B
Systemverilog
// DESCRIPTION: Verilator: SystemVerilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Anthony Donlon.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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t1 i_t1();
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endmodule
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module t1;
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int v = 0;
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logic [2:0] state;
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initial begin
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state = 2;
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casez (state)
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3'b11?, 3'b???: v++;
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default;
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endcase
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casez (state)
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3'b00?: $stop;
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3'b001, 3'b000: $stop;
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default;
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endcase
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casez (state)
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3'b111, 3'b0??: v++;
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3'b11?: $stop;
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default;
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endcase
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casez (state)
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3'b000, 3'b001, 3'b010, 3'b011: v++;
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3'b001: $stop;
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default;
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endcase
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casez (state)
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3'b000, 3'b001, 3'b010, 3'b011: v++;
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3'b011: $stop;
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default;
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endcase
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end
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endmodule
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