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75 lines
1.6 KiB
Systemverilog
75 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: SystemVerilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Anthony Donlon.
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// SPDX-License-Identifier: CC0-1.0
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// Fix bug4464
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module t;
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enum logic [1:0] {
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S00 = 'b00,
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S01 = 'b01,
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S10 = 'b10,
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S0X = 2'b0?,
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SX0 = 2'b?0
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} state;
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int v = 0;
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initial begin
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state = S01;
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unique case (state)
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S00: $stop;
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S01: v++;
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S10: $stop;
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endcase
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unique case (state)
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S00: $stop;
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default: v++; // default
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endcase
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unique case (state)
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2'd0: $stop;
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2'd1: v++;
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2'd2: $stop;
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endcase
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unique case (state)
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2'd0: $stop;
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2'd1: v++;
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2'd2: $stop;
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2'd3: $stop; // extra case
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endcase
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unique case (state) inside
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2'd0: $stop;
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2'd1: v++;
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[2'd2:2'd3]: $stop;
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endcase
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unique case (state) inside
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[S00:S10]: v++;
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endcase
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unique casez (state)
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S10: $stop;
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S0X: v++; // fully covered
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endcase
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unique casez (state)
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S10: $stop;
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S0X: v++;
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2'b11: $stop; // extra case
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endcase
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unique casez (state)
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S0X: v++;
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default: $stop;
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endcase
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case (state)
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S00: $stop;
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S01: v++;
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S10, 2'b11: $stop;
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endcase
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end
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endmodule
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