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61 lines
1.5 KiB
Systemverilog
61 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// A test case for struct signal bit selection.
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//
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// This test is to check that bit selection of multi-dimensional signal inside
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// of a packed struct works. Currently +: and -: blow up with packed structs.
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//
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// This file ONLY is placed into the Public Domain, for any use, without
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// warranty, 2013 by Jie Xu.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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typedef struct packed {
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logic [15:0] channel;
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logic [15:0] others;
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} buss_t;
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buss_t b;
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reg [7:0] a;
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reg [7:0] c;
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reg [7:0] d;
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union packed {
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logic [31:0] [7:0] idx;
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struct packed {
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logic [15:0] z, y, x;
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logic [25:0] [7:0] r;
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} nam;
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} gpr;
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reg [14:0] gpr_a;
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initial begin
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b = {16'h8765,16'h4321};
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a = b[19:12]; // This works
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c = b[8+:8]; // This fails
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d = b[11-:8]; // This fails
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`checkh(a, 8'h54);
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`checkh(c, 8'h43);
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`checkh(d, 8'h32);
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gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345;
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`checkh (gpr[255:255-14], 15'h091a);
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gpr_a = gpr.nam.z[15:1];
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`checkh (gpr_a, 15'h091a);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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