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24 lines
510 B
Systemverilog
24 lines
510 B
Systemverilog
// DESCRIPTION: Verilator: Test of select from constant
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//
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// This tests issue #508, bit select of constant fails
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// Note that if we declare "wire [0:0] b", this works just fine.
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wire a;
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wire b;
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assign b = 1'b0;
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assign a = b[0]; // IEEE illegal can't extract scalar
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endmodule
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