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92 lines
2.1 KiB
Systemverilog
92 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// A test case for struct signal bit selection.
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//
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// This test is to check that bit selection of multi-dimensional signal inside
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// of a packed struct works. Currently +: and -: blow up with packed structs.
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//
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// This file ONLY is placed into the Public Domain, for any use, without
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// warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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// Test IEEE 1800-2023 concat bit selects, function bit selects, method bit selects
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class Cls;
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static function logic [15:0] valf1ed();
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return 16'hf1ed;
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endfunction
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endclass
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module t(/*AUTOARG*/);
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Cls c;
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int q[$];
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logic [7:0] aa;
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logic [7:0] bb;
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logic [7:0] s8;
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logic s1;
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function logic [15:0] valf0ed();
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return 16'hf0ed;
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endfunction
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initial begin
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aa = 8'haa;
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bb = 8'hbb;
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s1 = {aa,bb}[8];
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`checkh(s1, 1'b0);
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s1 = {aa,bb}[9];
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`checkh(s1, 1'b1);
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s8 = {aa,bb}[11:4];
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`checkh(s8, 8'hab);
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s8 = {aa,bb}[4+:8];
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`checkh(s8, 8'hab);
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s8 = {aa,bb}[11-:8];
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`checkh(s8, 8'hab);
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s1 = valf0ed()[4];
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`checkh(s1, 1'b0);
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s1 = valf0ed()[5];
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`checkh(s1, 1'b1);
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s8 = valf0ed()[11:4];
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`checkh(s8, 8'h0e);
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s8 = valf0ed()[4+:8];
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`checkh(s8, 8'h0e);
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s8 = valf0ed()[11-:8];
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`checkh(s8, 8'h0e);
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c = new;
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s1 = c.valf1ed()[4];
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`checkh(s1, 1'b0);
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s1 = c.valf1ed()[5];
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`checkh(s1, 1'b1);
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s8 = c.valf1ed()[11:4];
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`checkh(s8, 8'h1e);
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s8 = c.valf1ed()[4+:8];
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`checkh(s8, 8'h1e);
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s8 = c.valf1ed()[11-:8];
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`checkh(s8, 8'h1e);
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q.push_front(32'h10ef);
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s1 = q.sum()[4];
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`checkh(s1, 1'b0);
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s1 = q.sum()[5];
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`checkh(s1, 1'b1);
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s8 = q.sum()[11:4];
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`checkh(s8, 8'h0e);
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s8 = q.sum()[4+:8];
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`checkh(s8, 8'h0e);
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s8 = q.sum()[11-:8];
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`checkh(s8, 8'h0e);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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